High speed low voltage driver

ABSTRACT

A high speed high and low voltage driver provides an output voltage without taxing a pumped voltage. The pumped voltage is used only when the output node has risen substantially to a supply voltage without draining the pumped voltage.

FIELD

[0001] The present invention relates generally to memory devices and inparticular the present invention relates to drivers for memory circuits.

BACKGROUND

[0002] Memory devices are available in a variety of styles and sizes.Some memory devices are volatile in nature and cannot retain datawithout an active power supply. A typical volatile memory is a DRAMwhich includes memory cells formed as capacitors. A charge, or lack ofcharge, on the capacitors indicate a binary state of data stored in thememory cell. Dynamic memory devices require more effort to retain datathan non-volatile memories, but are typically faster to read and write.

[0003] Non-volatile memory devices are also available in differentconfigurations. For example, floating gate memory devices arenon-volatile memories that use floating gate transistors to store data.The data is written to the memory cells by changing a threshold voltageof the transistor and is retained when the power is removed. Thetransistors can be erased to restore the threshold voltage of thetransistor. The memory may be arranged in erase blocks where all of thememory cells in an erase block are erased at one time. Thesenon-volatile memory devices are commonly referred to as flash memories.

[0004] The non-volatile memory cells are fabricated as floating gatememory cells and include a source region and a drain region that islaterally spaced apart from the source region to form an intermediatechannel region. The source and drain regions are formed in a commonhorizontal plane of a silicon substrate. A floating gate, typically madeof doped polysilicon, is disposed over the channel region and iselectrically isolated from the other cell elements by oxide. Forexample, gate oxide can be formed between the floating gate and thechannel region. A control gate is located over the floating gate and canalso made of doped polysilicon. The control gate is electricallyseparated from the floating gate by another dielectric layer. Thus, thefloating gate is “floating” in dielectric so that it is insulated fromboth the channel and the control gate.

[0005] In high performance flash memories, such as synchronous flashmemories, large loads are selected in the memory array during a read orwrite cycle. These loads must be selected in a very short time. Further,as components continue to shrink, and as operating power continues todecrease, components that consume less power are also needed. In highperformance memories, on each bitline of a memory array, there are gatesfor access transistors. In modem memories, there are on the order of4000 bitlines. Each bitline has a pass transistor between a globalbitline and the local bitline that is turned on for memory access in anactive cycle of the memory. Turning on 4000 transistors creates a largecapacitance that is turned on and off during each shift from bank tobank of a memory array during a read cycle of the memory. Typically,this row activation occurs every 20 nanoseconds. This can consume on theorder of 10 or more milliamps of current.

[0006] A pumped voltage circuit supplies a voltage V_(px) for the gatesof the pass transistors. This pumped voltage uses a supply voltage forthe memory as its source. As supply voltages continue to drop, presentlyto on the order of 1.6 to 1.8 volts, pumping V_(px) to about 5 voltsbecomes increasingly less power efficient, especially if there is acurrent drain due to the large capacitance of 4000 bitline transistors,since V_(px) is a pumped voltage and not a supply voltage. This pumpedvoltage is quickly drained of an unacceptable amount of current if it isused to supply the current required for loading 4000 bitlines. To supply10 milliamps from the pumped voltage circuit requires on the order of 30milliamps from V_(cc), which yields very low power efficiencies. Thecurrent that gets used for V_(px) is very expensive.

[0007] The gates on the pass transistors need to be pulled up to V_(cc)quickly to allow gate selection and activation within the very shorttime periods used in flash memories. Once a potential at or near V_(cc)is present at the gates, they need to be raised to a voltage slightlyabove V_(cc), but time is not as critical for the final increase.

[0008] For the reasons stated above, and for other reasons stated belowwhich will become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art fora driver that does not tax the current of a pumped gate voltage supply.

SUMMARY

[0009] The above-mentioned problems with gate selection and powerconsumption in flash memories and other problems are addressed by thepresent invention and will be understood by reading and studying thefollowing specification.

[0010] In one embodiment, a driver for a memory array includes an enablecircuit providing an enable signal, a pull down transistor having itsgate connected to the enable signal to ground an output node when theenable signal is disabled, and a pass transistor having its gateconnected through a first p-type pull-up transistor connected between apumped voltage and the gate of the pass transistor. An inverter isconnected between the enable circuit output and the pass transistor, anda second pull down transistor is connected between ground and the gateof the pass transistor. Two inverters are coupled in series between theoutput of the first inverter and the gate of the second pull downtransistor. A second p-type transistor is connected between the pumpedvoltage and the output node, the gate of the second p-type transistorconnected to the gate of the pass transistor.

[0011] In another embodiment, a driver for a memory array passtransistor block includes a first path for providing a supply voltage toan output node upon initiation of a read cycle, and a second path forproviding a pumped voltage to the output node after the output nodereceives the supply voltage, where the pumped voltage is greater thanthe supply voltage.

[0012] In yet another embodiment, a memory device includes an array ofmemory cells, control circuitry to read, write and erase the memorycells, and a driver circuit to control read access. The driver circuitincludes a first path for providing a supply voltage to the output uponinitiation of a read cycle, and a second path for providing a pumpedvoltage above the supply voltage after providing the supply voltage.

[0013] In still another embodiment, a flash memory device includes anarray of floating gate memory cells, control circuitry to read, writeand erase the floating gate memory cells, and a driver circuit tocontrol read access. The driver circuit includes a NAND gate providing aread signal, a pull down transistor having its gate connected to theread signal, to ground an output node when the read signal is disabled,a pass transistor having its gate connected through a first p-typepull-up transistor connected between a pumped voltage and the gate ofthe pass transistor, an inverter connected between the NAND gate outputand the pass transistor, a second pull down transistor connected betweenground and the gate of the pass transistor, a series connection of twoinverters connected between the output of the first inverter and thegate of the second pull down transistor, and a second p-type transistorconnected between the pumped voltage and the output node, the gate ofthe second p-type transistor connected to the gate of the passtransistor.

[0014] In yet another embodiment, a method of operating a circuitincludes holding an output node at a low potential, and maintaining apass transistor ready to supply the output node with a high potentialduring a read cycle. A supply voltage is passed to the output nodewithout using a pumped voltage upon initiation of the read cycle, and apumped voltage is passed to the output node to elevate the output nodevoltage above the supply voltage once the output node reaches the supplyvoltage.

[0015] In still yet another embodiment, a method of operating a readcycle in a memory includes supplying an output voltage to the gates ofan array of pass transistors of a memory array, the output voltageramped to a supply voltage without using a pumped voltage, and raisedabove a supply voltage with a pumped voltage.

[0016] In another embodiment, a method of providing a gate voltage forpass transistors of a memory array includes providing a supply voltagesubstantially immediately upon initiation of a read cycle, and delayingsupplying a pumped voltage to raise the gate voltage above the supplyvoltage until the gate voltage has reached the supply voltage.

[0017] Other embodiments are described and claimed.

BRIEF DESCRIPTION OF DRAWINGS

[0018]FIG. 1A is a block diagram of an embodiment of the presentinvention;

[0019]FIG. 1B is a circuit diagram of an embodiment of the presentinvention;

[0020]FIG. 2 is a block diagram of a memory according to an embodimentif the present invention; and

[0021]FIG. 3 is a block diagram of a memory according to anotherembodiment of the present invention.

DETAILED DESCRIPTION

[0022] In the following detailed description of the invention, referenceis made to the accompanying drawings that form a part hereof, and inwhich is shown, by way of illustration, specific embodiments in whichthe invention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention.

[0023] In addition, as the structures formed by embodiments inaccordance with the present invention are described herein, commonsemiconductor terminology such as N-type, P-type, N+ and P+ will beemployed to describe the type of conductivity doping used for thevarious structures or regions being described. The specific levels ofdoping are not believed to be germane to embodiments of the presentinvention; thus, it will be understood that while specific dopantspecies and concentrations are not mentioned, an appropriate dopantspecies with an appropriate concentration to its purpose, is employed.

[0024] The following detailed description is, therefore, not to be takenin a limiting sense, and the scope of the present invention is definedonly by the appended claims, along with the full scope of equivalents towhich such claims are entitled.

[0025]FIG. 1A shows an embodiment of a circuit 100 that is responsive toan enable signal 102, supplied from an external source. The enablesignal activates the output of the circuit 100. Circuit 100 comprises afirst branch 104 and a second branch 106. In one embodiment, the firstbranch supplies a supply voltage at an output node 108, ramping thesupply voltage up to a potential at or near the supply voltage for anappropriate circuit to be controlled by the output voltage, and thesecond branch supplies a pumped voltage above the supply voltage of thefirst branch.

[0026] First branch 104, when active, ramps the potential of output node108 to at or near a supply voltage. When second branch 106 is active, itramps the potential of the output node from the voltage at or near thesupply voltage to a potential above the current output voltage using apumped voltage supply. In one embodiment, the circuit switches from thefirst branch as a supply for the output node to the second branch as asupply for the output node once a predetermined threshold potential atthe output node is reached. In another embodiment, the circuit switchesfrom the first branch as a supply for the output node to the secondbranch as a supply for the output node once a predetermined time haselapsed with the first branch actively supplying a voltage to the outputnode. In one embodiment, the first branch ramps the output potentialquickly to at or near the supply voltage.

[0027] In one embodiment, a circuit 150 for providing an output voltageslightly above a supply voltage V_(cc) from an elevated voltage, V_(px)or V_(h), is shown in FIG. 1B. V_(px) is typically generated using apump circuit (not shown) and is greater than V_(cc). For purposes of thepresent invention, V_(px) can be generated using any technique includingan external supply. Circuit 150 includes a NAND gate 152 that has twoinputs. When the inputs to the NAND gate 152 are in a state to provide ahigh output from the NAND gate, pull down transistor 154, which is gateconnected to the NAND output, is turned on and the output voltage (node156) is pulled to ground. The output node 156 is connected to the gateof p-type transistor 158, which when NAND output is high, is turned onand passes a high voltage through transistor 158 to the gate of passtransistor 160, which is therefore turned on.

[0028] The same high voltage at the gate of p-type transistor 162 keepsit off. The output of NAND gate 152 is passed through a series of first,second, and third inverters 164, 166, and 168, respectively. Inverter164 output is low when NAND gate output is high, keeping a low potentialat node 170 connected to pass transistor 160. The signal is invertedtwice, in inverters 166 and 168, from low to high to low high again atthe output from inverter 168. In a steady state, transistor 171 is offwhen NAND gate 152 output is high, keeping node 172 high due to the passthrough of high potential through transistor 158.

[0029] Inverter 164 is in one embodiment a very strong PMOS inverter.The strength of the inverter 164 assists in raising the voltage at node156 to near V_(cc) in as fast a time as possible. The node 170 has aninherent rise time from its ground voltage to near V_(cc) that dependsupon the capacitance value seen at the node 156, that is the capacitancebuildup due to the load at node 156. Node 170 rises with an RC timeconstant which is the time constant for node 156 to charge to V_(cc).

[0030] The inputs to NAND gate 152 are provided by a pass transistorcontrol circuit such as circuit 174 shown in FIG. 1B. Pass transistorcontrol circuit determines when the output node voltage is to besupplied to the pass transistors, and is one embodiment dependent uponthe control circuitry for a memory. When the pass transistors are to beturned on, the control circuit 174 issues inputs to the NAND gate toforce the NAND gate output low. An enable circuit according to oneembodiment comprises a control circuit such as circuit 174 coupled to aNAND gate such as gate 152.

[0031] When the output of NAND gate 152 switches to low, transistor 154shuts off. Inverter 164 generates a high signal at node 170 which isvery quickly passed through pass transistor 160 as pass transistor 160is already on as discussed above. In one embodiment, the inverter 164 isa large inverter. In this embodiment, the size of inverter 164 creates astrong and fast ramp up of the voltage at the output node 156 to nearV_(cc). As the voltage ramps up to V_(cc) at output node 156, theincreasing voltage begins to and eventually fully shuts off transistor158. The output from inverter 164 also passes through time delayinverters 166 and 168, which in one embodiment are chosen in size to betrip point detectors. The first inverter 166 in one embodiment has askewed trip point. Inverter 166 does not trip until its input nearsV_(cc), for example, and then it trips the inverter 168 for anadditional delay before switching off the pass transistor 160 byoperation of the pull down transistor 171. The delays can therefore bechosen to allow the output node voltage to rise to near V_(cc) withoutusing current from the pumped voltage V_(px).

[0032] The delay on inverters 166 and 168 is controlled by the rise timeof node 170. For example, a typical rise time for nodes 156 and 170 tocharge to V_(cc) is about two (2) nanoseconds. In one embodiment, thedelays for the inverters are about 200 picoseconds each. The trip pointof inverter 166 is set high in one embodiment, and the inverter will nottrip until about one (1) nanosecond has elapsed. The inverters 166 and168 are in other words a detector. The line voltage at node 170 has toreach a certain threshold before the inverter 166 trips.

[0033] The trip points of inverters 166 and 168 are chosen in oneembodiment to allow the output node to charge to a predeterminedpotential level at or near V_(cc) before switching off pass transistor160 and completing a ramp to a potential above V_(cc) using smallertransistor 162 which draws current from the pumped voltage supply(V_(px)) as opposed to the supply voltage (V_(cc)).

[0034] Once the output signal from inverter 164 passes through theinverters 166 and 168, a high signal is presented at the gate oftransistor 171, which turns transistor 171 on, pulling node 172 toground and shutting off pass transistor 160. The low potential at node172 turns on transistor 162, and transistor 162 passes pumped voltageV_(px) to output node 156. However, since the output node 156 is alreadyat or near V_(cc), due to the ramp up from inverter 164 during the timedelay for shutting off pass transistor 160, the pumped voltage only hasto provide enough current to pull up node 156 from V_(cc) to a pointslightly above V_(cc), for example a threshold voltage, V_(t), aboveV_(cc), instead of a full potential of on the order of 5 volts.

[0035] The circuit ramps the output node 156 voltage quickly to at ornear V_(cc) without relying on the pumped voltage, drawing most of itsrequired current from V_(cc). The large inverter assists in ramping theoutput node voltage quickly to at or near V_(cc). When the outputvoltage reaches or nears V_(cc), depending upon the selectable timingfrom inverters 166 and 168, the remaining voltage necessary above V_(cc)is supplied by drawing on V_(px), but the initial ramp in the outputnode voltage is supplied by V_(cc).

[0036] A driver for the gates of pass transistors comprises in oneembodiment a circuit driven by V_(px). When the circuit is disabled,that is the memory is not in a read cycle, the output of the driver is aground voltage so that the gates of the pass transistors it drives areoff. The circuit is ready during its disable phase to quickly pass asupply voltage V_(cc) to the output when the circuit is enabled, and touse a pumped voltage to raise the output voltage above V_(cc) once itgets close to V_(cc), but without requiring a large current draw fromthe pumped voltage which supplies the driver. The driver of the presentembodiments obtains most of its current from the supply voltage, andonly relies on the pumped voltage for the extra current to push theoutput above the supply voltage. It is sufficient to drive the outputvoltage slightly above V_(cc), such as to about a threshold voltageV_(t) above V_(cc). Current usage from the pumped voltage drops to about{fraction (1/7)} to ⅛ of previous solutions.

[0037] Flash memories using a voltage sensing in order to perform readand write operations are amenable to use with the driver describedabove. In one embodiment, a driver such as that described above providesthe gate voltage for the pass transistors 202 of memory device 200 as isshown in FIG. 2. The pass transistors connect global bitlines 204 tosense amplifiers 206 of memory device 200. Memory array 208 is readthrough the use of the sense amps as is well known in the art. A drivercircuit, such as driver circuit 150 described above, provides the gatevoltage for the pass transistors. The driver provides a supply voltagenearly immediately upon enabling of the driver circuit. The drivercircuit then provides a voltage slightly above the supply voltage,delayed to allow the voltage to rise to at or near V_(cc), after thegate voltage ramps up to at or near V_(cc) without requiring a drain onthe current of the pumped voltage that supplies the driver circuit.

[0038]FIG. 3 is a functional block diagram of a memory device 300, ofone embodiment of the present invention, which is coupled to a processor310. The memory device 300 and the processor 310 may form part of anelectronic system 320. The memory device 300 has been simplified tofocus on features of the memory that are helpful in understanding thepresent invention. The memory device includes an array of memory cells330. The memory array 330 is arranged in banks of rows and columns.

[0039] An address buffer circuit 340 is provided to latch addresssignals provided on address input connections A0-Ax 342. Address signalsare received and decoded by row decoder 344 and a column decoder 346 toaccess the memory array 330. It will be appreciated by those skilled inthe art, with the benefit of the present description, that the number ofaddress input connections depends upon the density and architecture ofthe memory array. That is, the number of addresses increases with bothincreased memory cell counts and increased bank and block counts.

[0040] The memory device reads data in the array 330 by sensing voltageor current changes in the memory array columns using sense/latchcircuitry 350. The sense/latch circuitry, in one embodiment, is coupledto read and latch a row of data from the memory array. Sense/latchcircuitry 350 in one embodiment includes a driver circuit for the passtransistors of the sense/latch circuitry, such as that described above.Data input and output buffer circuitry 360 is included forbi-directional data communication over a plurality of data (DQ)connections 362 with the processor 310.

[0041] Command control circuit 370 decodes signals provided on controlconnections 372 from the processor 310. These signals are used tocontrol the operations on the memory array 330, including data read,data write, and erase operations. The flash memory device has beensimplified to facilitate a basic understanding of the features of thememory. A more detailed understanding of internal circuitry andfunctions of flash memories are known to those skilled in the art.

[0042] Finally, it will be understood that the number, relative size andspacing of the structures depicted in the accompanying figures areexemplary only, and thus were selected for ease of explanation andunderstanding. Therefore such representations are not indicative of theactual number or relative size and spacing of an operative embodiment inaccordance with the present invention.

CONCLUSION

[0043] A driver for a flash memory has been described that includes acombined voltage obtained mostly from a supply voltage, and onlypartially from a pumped voltage, so as to not tax the pumped voltage bydrawing too much current therefrom.

[0044] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement, which is calculated to achieve the same purpose,may be substituted for the specific embodiment shown. This applicationis intended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

What is claimed:
 1. A driver for a memory array, comprising: an enablecircuit providing an enable signal; a pull down transistor having itsgate connected to the enable signal, to ground an output node when theenable signal is disabled; a pass transistor having its gate connectedthrough a first p-type pull-up transistor connected between a pumpedvoltage and the gate of the pass transistor; an inverter connectedbetween the enable circuit output and the pass transistor; a second pulldown transistor connected between ground and the gate of the passtransistor; a series connection of two inverters connected between theoutput of the first inverter and the gate of the second pull downtransistor; and a second p-type transistor connected between the pumpedvoltage and the output node, the gate of the second p-type transistorconnected to the gate of the pass transistor.
 2. The driver of claim 1,wherein the pass transistor is very large compared to the second p-typetransistor.
 3. The driver of claim 1, wherein the first inverter is verylarge compared to the second and the third inverters.
 4. The driver ofclaim 1, wherein the pumped voltage is at least a threshold voltageabove the supply voltage.
 5. The driver of claim 1, wherein the secondand third inverters are selected as trip point inverters to delay a turnon of the second p-type transistor until after turn on of the passtransistor.
 6. The driver of claim 1, wherein the enable circuitcomprises: a NAND gate; and a control circuit providing inputs to theNAND gate.
 7. A driver for a memory array pass transistor block, thedriver comprising: a first path for providing a supply voltage to anoutput node upon initiation of a read cycle; and a second path forproviding a pumped voltage to the output node after the output nodereceives the supply voltage, where the pumped voltage is greater thanthe supply voltage.
 8. The driver of claim 7, wherein the first pathcomprises a large pass transistor connected to a supply voltage, thepass transistor passing the supply voltage to the output node.
 9. Thedriver of claim 7, wherein the second path comprises a small passtransistor passing the pumped voltage to the output node after the passtransistor passes the supply voltage to the output node.
 10. The driverof claim 7, and further comprising: a pair of delay inverters, the delayinverters delaying the turn on of the small pass transistor for apredetermined time from when the pass transistor begins passing thesupply voltage.
 11. A memory device comprising: an array of memorycells; and control circuitry to read, write and erase the memory cells;and a driver circuit to control read access, the driver circuitcomprising: a first path for providing a supply voltage to the outputupon initiation of a read cycle; and a second path for providing apumped voltage above the supply voltage after providing the supplyvoltage.
 12. A flash memory device comprising: an array of floating gatememory cells; and control circuitry to read, write and erase thefloating gate memory cells; and a driver circuit to control read access,the driver circuit comprising: a NAND gate providing a read signal; apull down transistor having its gate connected to the read signal, toground an output node when the read signal is disabled; a passtransistor having its gate connected through a first p-type pull-uptransistor connected between a pumped voltage and the gate of the passtransistor; an inverter connected between the NAND gate output and thepass transistor; a second pull down transistor connected between groundand the gate of the pass transistor; a series connection of twoinverters connected between the output of the first inverter and thegate of the second pull down transistor; and a second p-type transistorconnected between the pumped voltage and the output node, the gate ofthe second p-type transistor connected to the gate of the passtransistor.
 13. The driver of claim 12, wherein the pass transistor isvery large compared to the second p-type transistor.
 14. The driver ofclaim 12, wherein the first inverter is very large compared to thesecond and the third inverters.
 15. The driver of claim 12, wherein thepumped voltage is at least a threshold voltage above the supply voltage.16. A method of operating a circuit, comprising: holding an output nodeat a low potential; maintaining a pass transistor ready to supply theoutput node with a high potential during a read cycle; passing a supplyvoltage to the output node without using a pumped voltage uponinitiation of the read cycle; and passing a pumped voltage to elevatethe output node above the supply voltage once the output node reachesthe supply voltage.
 17. The method of claim 16, wherein holding anoutput node at low potential comprises pulling the node to groundthrough a transistor.
 18. The method of claim 16, wherein maintaining apass transistor ready to supply the output node comprises: maintaining ap-type transistor on feeding a high voltage to the gate of the passtransistor, the p-type transistor gate voltage connected to the outputnode.
 19. The method of claim 16, wherein supplying a supply voltagecomprises inverting the output node signal with a large inverter, andsupplying the inverted signal to the pass transistor.
 20. The method ofclaim 16, wherein supplying a pumped voltage comprises: delaying a turnon of a pull down transistor that connects a pumped voltage to theoutput node until the output node has reached a supply voltagepotential.
 21. The method of claim 16, wherein supplying the pumpedvoltage further comprises connecting the pumped voltage through a p-typetransistor that turns on after the delay.
 22. The method of claim 16,wherein the p-type transistor draws a small current upon activation. 23.A method of operating a read cycle in a memory, comprising: supplying anoutput voltage to the gates of an array of pass transistors of a memoryarray, the output voltage ramped to a supply voltage without using apumped voltage, and raised above a supply voltage with a pumped voltage.24. The method of claim 23, wherein ramping the output voltage to asupply voltage comprises: holding an output node at a low potential;maintaining a pass transistor ready to supply the output node with ahigh potential during a read cycle; and supplying a supply voltage tothe output node without using a pumped voltage upon initiation of theread cycle.
 25. The method of claim 23, wherein raising the outputvoltage above a supply voltage comprises: supplying a pumped voltage toelevate the output node above the supply voltage once the output nodereaches the supply voltage.
 26. The method of claim 25, whereinsupplying the pumped voltage comprises: turning off the pass transistor;and turning on a small transistor connected between the pumped voltageand the output node once the pass transistor is turned off.
 27. Themethod of claim 23, wherein the pumped voltage is coupled to raise theoutput voltage above the supply voltage after the output voltage hasreached a predetermined potential.
 28. The method of claim 23, whereinthe pumped voltage is coupled to raise the output voltage above thesupply voltage after the output voltage has been ramping to the supplyvoltage for a predetermined time period.
 29. A method of providing agate voltage for pass transistors of a memory array, comprising:providing a supply voltage substantially immediately upon initiation ofa read cycle; delaying supplying a pumped voltage to raise the gatevoltage above the supply voltage until the gate voltage hassubstantially reached the supply voltage.
 30. The method of claim 29,wherein delaying supplying a pumped voltage comprises passing a readsignal through a series of inverters chosen to delay coupling the pumpedvoltage to the gate until it has risen to the supply voltage level. 31.A method for supplying an output voltage, comprising: supplying anoutput voltage to the gates of an array of pass transistors of a memoryarray, the output voltage ramped to a supply voltage without using apumped voltage, and raising the output voltage above the supply voltagewith a pumped voltage after the output voltage receives the supplyvoltage, wherein the pumped voltage is greater than the supply voltage.32. The method of claim 31, wherein raising the output voltage isaccomplished after the supply voltage reaches a predetermined thresholdpotential.
 33. The method of claim 31, wherein raising the outputvoltage is accomplished after the supply voltage has been supplied for apredetermined time period.
 34. A circuit for providing an output voltageat an output node, comprising: first and second branches, the firstbranch coupled to the output node to raise a potential at the outputnode to approximately a supply voltage, and the second branch coupled tothe output node once the output node voltage has reached a predeterminedpotential threshold, to raise the potential of the output node above thethreshold using a pumped voltage.
 35. The circuit of claim 34, whereinthe first branch comprises: an inverter; and a pass gate connected topass the inverter output to the output node.
 36. The circuit of claim34, wherein the second branch comprises: a p-type transistor connectedbetween the pumped voltage and the output node to pass the pumpedvoltage to the output node.
 37. The circuit of claim 36, wherein thesecond branch further comprises: a pair of trip point inverters to delaya turn on of the p-type transistor until the output voltage reaches thepredetermined potential.
 38. The circuit of claim 34, wherein the firstbranch comprises: a first inverter; and a pass gate connected to passthe first inverter output to the output node; and wherein the secondbranch comprises: a p-type transistor connected between the pumpedvoltage and the output node to pass the pumped voltage to the outputnode; and second and third inverters connected to delay turn on of thep-type transistor.
 39. The circuit of claim 38, wherein the pass gate isvery large compared to the p-type transistor.
 40. The driver of claim38, wherein the first inverter is very large compared to the second andthe third inverters.
 41. The driver of claim 38, wherein the pumpedvoltage is at least a threshold voltage above the supply voltage. 42.The driver of claim 34, wherein the second and third inverters areselected as trip point inverters to delay a turn on of the second p-typetransistor until after turn on of the pass transistor.
 43. A circuit forproviding an output voltage at an output node, comprising: first andsecond branches, the first branch coupled to the output node to raise apotential at the output node to approximately a supply voltage, and thesecond branch coupled to the output node once a predetermined timeperiod has elapsed, to raise the potential of the output node above thethreshold using a pumped voltage.
 44. A circuit, comprising: a firstbranch and a second branch connectable between an enable signal and anoutput node; wherein the first branch comprises a supply voltage and thesecond branch provides a pumped voltage, the circuit selecting whichbranch to supply to the output node depending upon the potential at theoutput node.